Example implementation of PXROS-HR trap handler

#define TC_CORE_ID          0xFE1C  /* "Core Identification" */
#define TC_CORE_ID_MASK     0x7     /* "Core Identification field mask" */

PxBool_t Trap_Hnd_01(PxTrapTin_t trapTin, PxUInt_t hnd_arg, PxUInt_t runtaskId,
                     PxUInt_t dstr, PxUInt_t *deadd, TC_CSA_t *csa);
{
    /* Get core ID from core register value 6 corresponds to core 5 (Errata) */
    PxUInt_t coreId = __MFCR(TC_CORE_ID) & TC_CORE_ID_MASK;
    if (coreId == 6)
        coreId--;

    PxTask_t task_id = PxTaskIdSet(runtaskId);
    TC_CSA_t *csa_upper;
    csa_upper = CSA2PTR(csa->lower.PCXI);

    if (PxTaskIdIsValid(task_id))
    {
        /* Different solution on different cores */
        switch (coreId)
        {
        case 0: /* Core 0 */
            switch (trapTin.t.tin)
            {
            case PRIV: /* TIN 1 - Privileged Instruction */
                /* Code to handle PRIV */
                return true;
            case MPR: /* TIN 2 - Memory Protection Read */
                /* Code to handle MPR */
                return true;
            case MPW: /* TIN 3 - Memory Protection Write */
                /* Code to handle MPW */
                return true;
            }
            /* Other TINs not handled */
            break;

        case 1: /* Core 1 */
            /* Code to handle all TINs */
            return true;

        default: /* Other cores */
            /* Trap not handled on other cores */
            return false;
        }
    }
    return false;
}