Introduction

In the context of multi-core embedded systems, maintaining data cache coherency is vital for ensuring the accuracy and consistency of shared data across multiple processing cores. Data cache coherency refers to the mechanism that guarantees all cores have a synchronized and consistent view of shared data, even in the presence of private caches. This mechanism involves managing data transfers and invalidations between caches to ensure that any modifications made by one core are visible to others.

However, in the Infineon Tricore architecture, there is no hardware mechanism provided to ensure data cache coherency between cores. To address this limitation, the PXROS-HR implements its own software mechanism for achieving data cache coherency.

This document serves as an overview of how PXROS-HR ensures the coherency of cached data during inter-core communication. It also highlights the limitations of the current implementation, specifically when using the message envelope or directly accessing shared data.