PXROS-HR data coherency implementation

Standard messages

To maintain data coherency during message transmission, PXROS-HR employs a mechanism that ensure the integrity of those data. This mechanism specifically operates when sending (PxMsgSend()) or awaiting (PxMsgAwaitRel()) cross-core messages over cached memory segments located at memory addresses 9xxx_xxxxH and 8xxx_xxxxH (see Memory Overview for more details). It is important to mentioned that since in-core transfers utilize a local cache, there is no need to address data incoherency. Thus the cache coherency mechanism is not applied in such transfers. Within the PXROS-HR kernel, operations such as cache write-back and invalidation are managed between message transmission and reception to guarantee the coherency of the message payload.

The following cache instructions are involved in the data cache handling:

CACHEA.WI

Writeback any modified data and then invalidate the line in the data cache.

CACHEI.I

Invalidate the cache line if present in the data cache. There is no writeback of any dirty data in the cache line prior to invalidation.

Performance impact

Considering the absence of alternative hardware mechanisms, it is required to apply those instructions to every cache line across the message buffer size.The performance impact of this process may be affected by whether the given cache line is present in the cache and modified. As each cache line needs to be managed individually, it can be stated that the worst case impact is roughly proportional to the ratio of the message buffer size to the cache line size, which is 32 bytes.

Message envelope

When utilizing message envelopes, special attention must be given to ensure data coherency. Unlike data transfer using standard messages, message envelopes facilitate sharing a portion of memory between tasks. To guarantee data coherency in this scenario, the following rules should be followed:

Release message first

Ensure that the task providing the memory region for the message envelope (sender) accesses the memory region only after the recipient has released the message. PXROS-HR supports this check through the await-release mechanism.

One-to-one relationship

Ensure a one-to-one relationship, which means that any memory region can be exclusively wrapped in an envelope and sent to only one user (recipient) at a time.

Memory region sharing

Avoid sharing the same memory region actively used for message envelopes with other tasks simultaneously, such as through extended memory areas.

Access shared data

When it comes to directly shared data, such as a memory block that is shared among tasks using extended memory regions, it is important to note that PXROS-HR does not implement or perform any data coherency checks in this scenario. The responsibility for maintaining coherency of the shared data falls upon the application/tasks themselves.

It is crucial for the tasks accessing the shared memory block to carefully manage and synchronize their operations to ensure data integrity and coherency. Failure to do so may result in inconsistencies or race conditions in the shared data. Therefore, it is recommended to employ appropriate synchronization mechanisms, such as locks or semaphores, to coordinate access to the shared memory and maintain data coherency manually.