Cache memory overview

The Program Cache operates as a two-way set-associative cache with a Least-Recently-Used (LRU) replacement algorithm. Each PCACHE line consists of 256 bits of instruction along with associated ECC bits.

When the CPU performs a program fetch access to a cacheable memory segment (assuming the PCACHE is not bypassed), it targets the PCACHE. If the requested address and its associated instruction are found in the cache (Cache Hit), the instruction is directly passed to the CPU Fetch Unit without any wait states. However, if the address is not found in the cache (Cache Miss), the PMI cache controller initiates a cache refill sequence, and wait states are incurred while the cache line is being refilled.

The DCACHE is a type of cache called Two-way set-associative, which uses a Least-Recently-Used (LRU) replacement algorithm. Each line in the cache contains 256 bits of data and ECC bits. For every line, there is a single valid bit and a single dirty bit associated with it.

When the CPU accesses data from a memory segment that can be cached, it targets the DCache. If the requested address and its associated data are already present in the cache (Cache Hit), the data is directly passed to/from the CPU Load-Store Unit without any wait states. On the other hand, if the address is not found in the cache (Cache Miss), the DMI cache controller initiates a cache refill process, and wait states are incurred while the cache line is refilled.

The data cache follows a writeback approach. Whenever the CPU writes to a cacheable location, the data is merged with the corresponding cache line and is not immediately written to the main memory. Each cache line has a 'dirty' bit associated with it, indicating that the data in that cache line has been modified. In case of a CPU load-store access resulting in a cache miss and all the potential cache ways that could hold the requested cache line are valid, the cache uses the LRU replacement algorithm to choose one cache line for eviction. The selected line is then checked to see if it has been modified by examining its dirty bit. If the line has not been modified, it is discarded, and the refill sequence is started immediately. However, if the line has been modified, the dirty data is first written back to the main memory before the refill process begins.

Data Cache refills always involve fetching the entire cache line, starting with the critical double-word of the DCache line. Each refill process only affects one cache line at a time.

Both data and program cache can be bypassed. By default, after a reset, the caches are bypassed. When the cache bypass is enabled, every data access or instruction fetch requested by the CPU to a cacheable address will always result in a Cache Miss. When cache bypass is enabled, both data accesses and instruction fetch requests to cacheable addresses behave identically to accesses or fetches from non-cacheable addresses.

The cache memory can be mapped into the CPU’s address space, making it contiguous with the DSPR/PSPR memories. Once mapped, the cache memories function just like the PSPR/DSPR memories, and they can be used as standard memory.