Memory access latency
The following table describes the CPU access times to local resource in CPU clock cycles for the AURIXâ„¢ TC3xx Platform.
In the case of load or fetch accesses, the access times are minimum CPU stall cycles to complete the access. If there is a conflict for the resource accessed there may be additional stall cycles till the conflicting access completes.
For write access, the access times are the maximum for a sequence of such access (non-conflicting). If there is a conflict for the resource accessed there may be additional stall cycles till the conflicting access completes.
| Access type | CPU stall cycles |
|---|---|
Data read access from DSPR |
0 |
Data write access to DSPR |
0 |
Data read access from DCACHE |
0 |
Data read access from PCACHE |
0 |
Instruction fetch from DSPR |
6 |
Data read access from DLMU |
1 |
Data write access to DLMU |
2 |
Instruction fetch from DLMU |
7 |
Data read access from PSPR |
6 |
Data write access to PSPR |
7 |
Instruction fetch from PSPR |
0 |
Data read access from PFlash |
3 + PFlash Wait States |
Instruction fetch from PFlash (buffer miss) |
2 + PFlash Wait States |
Instruction fetch from PFlash (buffer hit) |
2 |