Memory overview

The simplified Infineon TC3xx memory model illustrates the interconnection between the CPU core and the memory. All bus master agents, including the CPU cores, have the ability to address memories using identical addresses. The system address map is generally valid for all TriCore CPUs and other bus master agents on the chip. This means that all system resources can be accessed from any TriCore CPU or other bus master agent.

As shown in the above depiction, the cached access to the RAM or PFLASH is specifically addressed within the 9xxx_xxxx_H and 8xxx_xxxx_H address range. These memory regions are the focus of PXROS-HR when dealing with data cache coherency. For detailed information regarding memory access penalties, please refer to the appendix on Memory Access Latency. It provides additional insights into the specific penalties associated with memory access.