Initial state upon a trap

Initial state upon a HW trap

Detailed information can be found in [1].

The initial state when a HW trap occurs is defined as follows:

  • The upper context is saved.

  • The return address in A[11] is updated.

  • The TIN is loaded into D[15].

  • The stack pointer in A[10] is set to the Interrupt Stack Pointer (ISP) when the processor was not previously using the interrupt stack (in case of PSW.IS = 0). The stack pointer bit is set for using the interrupt stack: PSW.IS = 1.

  • The I/O mode is set to Supervisor mode, which means all permissions are enabled: PSW.IO = 10B.

  • The current Protection Register Set is set to 0: PSW.PRS = 000B.

  • The Call Depth Counter (CDC) is cleared, and the call depth limit is set for 64: PSW.CDC = 0000000B.

  • Call Depth Counter is enabled, PSW.CDE = 1.

  • PSW Safety bit is set to value defined in the SYSCON register. PSW.S = SYSCON.TS.

  • Write permission to global registers A[0], A[1], A[8], A[9] is disabled: PSW.GW = 0.

  • The interrupt system is globally disabled: ICR.IE = 0. The 'old' ICR.IE and ICR.CCPN are saved into PCXI.PIE and PCXI.PCPN respectively. ICR.CCPN remains unchanged.

  • The trap vector table is accessed to fetch the first instruction of the trap handler.

Although traps leave the ICR.CCPN unchanged,their handlers still begin execution with interrupts disabled. They can therefore perform critical initial operations without interruptions, until they specifically re-enable interrupts.

For the non-recoverable FCU trap, the initial state is different. The upper context cannot be saved. Only the following states are guaranteed:

  • The TIN is loaded into D[15].

  • The stack pointer in A[10] is set to the Interrupt Stack Pointer (ISP) when the processor was not previously using the interrupt stack (in case of PSW.IS == 0).

  • The I/O mode is set to Supervisor mode (all permissions are enabled: PSW.IO = 10B).

  • The current Protection Register Set is set to 0: PSW.PRS = 000B.

  • PSW Safety bit is set to value defined in the SYSCON register: PSW.S = SYSCON.TS.

  • The interrupt system is globally disabled: ICR.IE = 0. ICR.CCPN remains unchanged.

  • The trap vector table is accessed to fetch the first instruction of the FCU trap handler.

Initial state after the PXROS-HR trap prologue

A few things differ from a default HW trap when using PXROS-HR. The PXROS-HR prologue takes care of:

  1. The lower context is saved

  2. DSTR and DEADD registers are read

  3. DSTR is cleared

  4. Interrupts are enabled

For Asynchronous traps, PXROS-HR does not read the DATR register, and the user always has to read the DATR register to get the reason of the trap.

Initial state upon a user trap handler

Initial state after executing the default PXROS-HR trap handler — base state for a user trap handler:

  • Interrupts are enabled

  • If ICR.CCPN was 0, set to 1

  • Status register values from the HW trap’s initial state are no longer valid. Therefore, the six arguments of the user trap handler are used instead. These are passed to a user trap handler to identify what happened (more at User trap handler definition).

  • Interrupt Stack Pointer (ISP) is used

  • I/O mode is set to Supervisor

  • The current Protection Register Set is set to 3 (combines the address spaces of the kernel and the task that installed the user trap handler)

  • The Call Depth Counter (CDC) is set to 1

The rest remains the same as described above.