Trap descriptions
Details can be found in Infineon user manual [1].
In the following tables:
-
TIN = Trap Identification Number
-
Synch. = Synchronous / Asynch. = Asynchronous
-
HW = Hardware / SW = Software.
MMU traps (Trap Class 0)
For those implementations that include a Memory Management Unit (MMU), Trap class 0 is reserved for MMU traps. There are two traps within this class, VAF and VAP.
| TIN | Name | Synch. / Asynch. | HW / SW | Definition |
|---|---|---|---|---|
0 |
VAF |
Synch. |
HW |
Virtual Address Fill |
1 |
VAP |
Synch. |
HW |
Virtual Address Protection |
Internal protection traps (Trap Class 1)
Trap class 1 is for traps related to the internal protection system. The memory protection traps in this class, MPR, MPW, and MPX, are for the range-based protection system and are independent of the page-based VAP protection trap of trap class 0. All memory protection traps (MPR, MPW, MPX, MPP, and MPN), are based on the virtual addresses that undergo direct translation.
| TIN | Name | Synch. / Asynch. | HW / SW | Definition |
|---|---|---|---|---|
1 |
PRIV |
Synch. |
HW |
Privileged Instruction |
2 |
MPR |
Synch. |
HW |
Memory Protection Read |
3 |
MPW |
Synch. |
HW |
Memory Protection Write |
4 |
MPX |
Synch. |
HW |
Memory Protection Execute |
5 |
MPP |
Synch. |
HW |
Memory Protection Peripheral Access |
6 |
MPN |
Synch. |
HW |
Memory Protection Null Address |
7 |
GRWP |
Synch. |
HW |
Global Register Write Protection |
Instruction errors (Trap Class 2)
Trap class 2 is for signalling various types of instruction errors. Instruction errors include errors in the instruction opcode, in the instruction operand encodings, or for memory accesses, in the operand address.
| TIN | Name | Synch. / Asynch. | HW / SW | Definition |
|---|---|---|---|---|
1 |
IOPC |
Synch. |
HW |
Illegal Opcode |
2 |
UOPC |
Synch. |
HW |
Unimplemented Opcode |
3 |
OPD |
Synch. |
HW |
Invalid Operand specification |
4 |
ALN |
Synch. |
HW |
Data Address Alignment |
5 |
MEM |
Synch. |
HW |
Invalid Local Memory Address |
Context management (Trap Class 3)
Trap class 3 is for exception conditions detected by the context management subsystem, in the course of performing (or attempting to perform) context save and restore operations connected to function calls, interrupts, traps, and returns.
| TIN | Name | Synch. / Asynch. | HW / SW | Definition |
|---|---|---|---|---|
1 |
FCD |
Synch. |
HW |
Free Context List Depletion (FCX = LCX) |
2 |
CDO |
Synch. |
HW |
Call Depth Overflow |
3 |
CDU |
Synch. |
HW |
Call Depth Underflow |
4 |
FCU |
Synch. |
HW |
Free Context List Underflow (FCX = 0) |
5 |
CSU |
Synch. |
HW |
Call Stack Underflow (PCX = 0) |
6 |
CTYP |
Synch. |
HW |
Context Type (PCXI.UL wrong) |
7 |
NEST |
Synch. |
HW |
Nesting Error: RFE with non-zero call depth |
System bus and peripheral errors (Trap Class 4)
Trap class 4 is for system bus and peripheral errors.
| TIN | Name | Synch. / Asynch. | HW / SW | Definition |
|---|---|---|---|---|
1 |
PSE |
Synch. |
HW |
Program Fetch Synchronous Error |
2 |
DSE |
Synch. |
HW |
Data Access Synchronous Error |
3 |
DAE |
Asynch. |
HW |
Data Access Asynchronous Error |
4 |
CAE |
Asynch. |
HW |
Coprocessor Trap Asynchronous Error |
5 |
PIE |
Synch. |
HW |
Program Memory Integrity Error |
6 |
DIE |
Asynch. |
HW |
Data Memory Integrity Error |
7 |
TAE |
Asynch. |
HW |
Temporal Asynchronous Error |
Assertion traps (Trap Class 5)
Trap class 5 is for assertation traps.
| TIN | Name | Synch. / Asynch. | HW / SW | Definition |
|---|---|---|---|---|
1 |
OWF |
Synch. |
SW |
Arithmetic Overflow |
2 |
SOVF |
Synch. |
SW |
Sticky Arithmetic Overflow |