Analyzing trap root cause

TINs (Trap Identification Number) are used for detailed analysis of the trap root cause in aid of data in DSTR, DATR, and DEADD registers. Traps are divided into 8 classes, each with similar types of traps. Each class has a further division to identify what happened in detail. This division is based on specific TINs. The corresponding description is in chapter Trap descriptions.

DMI Trap Generation (DMI = Data Memory Interface) can be found in Aurix target specification chapter 5.3.6.4.4 [2]. Register description of DSTR, DATR, and DEADD in the same chapter below. These three registers are used to aid with the localization of faults. DSTR meaning is to inform about which synchronous error caused a trap. DATR meaning is to inform about which asynchronous error caused a trap. And the value of DEADD is an address that tells detailed information about the fault. The DEADD register contents are only valid when either the DATR or DSTR register is non-zero.

For Asynchronous traps, PXROS-HR does not read the DATR register, and the user always has to read the DATR register to get the reason of the trap.

For example, if a task tries to write at address 0x8 and its memory protection unit is not set for that address, this write (store instruction) causes a trap. DSTR is updated, and the MPE bit is set. In the DEADD register is the value of the address where the task tried to write (0x8).

Tab. 1. Information contained in 'DSTR' register
Bit Bit Name Description

SRE

Scratch Range Error

Data access to data scratch memory region outside of physically implemented memory

LBE

Load Bus Error

Data load from bus causing error

CRE

Cache Refill Error

Bus error during cache refill

DTME

DTAG MSIST Error

Access to memory mapped DTAG range outside of physically implemented memory

LOE

Load Overlay Error

Load to invalid overlay address

SDE

Segment Difference Error

Load or store access where base address is in different segment to access address

SCE

Segment Crossing Error

Load or store access across segment boundary

CAC

CSFR Access Error

Load or store to local CSFR space

MPE

Memory Protection Error

Data access violating memory protection.

CLE

Context Location Error

Context operation to invalid location

ALN

Alignment Error

Data access causing alignment error

Tab. 2. Information contained in 'DATR' register
Bit Bit Name

SBE

Store Bus Error

CWE

Cache Writeback Error

CFE

Cache Flush Error

SOE

Store Overlay Error